1. Field of the Invention
The present invention relates to wiring boards and methods of manufacturing the same. In more detail, embodiments of the present invention relate to wiring boards having a conductor post and methods of manufacturing such wiring boards.
2. Description of Related Art
In recent years, as a high-density packaging technique, for example, a C4 (controlled collapse chip connection) method has been adopted. Wiring boards utilized in C4 methods have surface that is covered by a solder resist layer, and wherein a bump (conductor post) is vertically arranged, in an optionally bored opening in the solder resist layer, and electrically connected to a conductor layer within the wiring board. Such wiring boards that may be used the C4 methods, and which have such a connection with the bump, may attain bump pitches as low as 145 μm with the progress of high-purity packaging. However, it is expected that high-density packaging will further proceed in the future, and may require narrower bump pitches (for example, 100 μm). These narrower bump pitches require smaller diameter openings to be bored in the solder resist layer. On the other hand, the required height of bumps may be kept constant in the future. That is, it may be necessary for bumps to have shapes with higher aspect ratios.
Current conventional technologies are described in Japanese Patent Publication No. H9-205096, Japanese Patent Publication No. JP-2009-164442, Japanese Patent Application No. JP-2006-279062, U.S. Pat. No. 7,216,424, U.S. Pat. No. 6,229,220, and U.S. Patent Publication No. 2005/0029110.